The present invention relates to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having transistors with small and/or densely packed and/or multi-sided active lines.
Currently, deep-submicron complementary metal oxide semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) circuits. Over the last two decades, reduction in the size of CMOS transistors has been a principal focus of the microelectronics industry.
Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally either bulk semiconductor-type devices or silicon-on-insulator (SOI)-type devices. Most integrated circuits are fabricated in a CMOS process on a bulk semiconductor substrate.
In bulk semiconductor-type devices, transistors, such as, MOSFETs, are built on the top surface of a bulk substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions. As transistors become smaller, the body thickness of the transistor (or thickness of depletion layer below the inversion channel) must be scaled down to achieve superior short-channel performance.
Conventional SOI-type devices include an insulative substrate attached to a thin-film semiconductor substrate that contains transistors similar to the MOSFETs described with respect to bulk semiconductor-type devices. The insulative substrate generally includes a buried insulative layer above a lower semiconductor base layer. The transistors on the insulative substrate have superior performance characteristics due to the thin-film nature of the semiconductor substrate and the insulative properties of the buried insulative layer. In a fully depleted (FD) MOSFET, the body thickness is so small that the depletion region has a limited vertical extension, thereby eliminating link effect and lowering hot carrier degradation. The superior performance of SOI devices is manifested in superior short-channel performance (i.e., resistance to process variation in small size transistor), near-ideal subthreshold voltage swing (i.e., good for low off-state current leakage), and high saturation current.
Ultra-large-scale integrated (ULSI) circuits generally include a multitude of transistors, such as, more than one million transistors and even several million transistors that cooperate to perform various functions for an electronic component. The transistors are generally complementary metal oxide semiconductor field effect transistors (CMOSFETs) which include a gate conductor disposed between a source region and a drain region. The gate conductor is provided over a thin gate oxide material. Generally, the gate conductor can be a metal, a polysilicon, or polysilicon/germanium (SixGe(1xe2x88x92x)) material that controls charge carriers in a channel region between the drain and the source to turn the transistor on and off. The transistors can be N-channel MOSFETs or P-channel MOSFETs.
Generally, it is desirous to manufacture smaller transistors to increase the component density on an integrated circuit. It is also desirous to reduce the size of integrated circuit structures, such as vias, conductive lines, capacitors, resistors, isolation structures, contacts, interconnects, etc. For example, manufacturing a transistor having a reduced gate length (a reduced width of the gate conductor) can have significant benefits. Gate conductors with reduced widths can be formed more closely together, thereby increasing the transistor density on the IC. Further, gate conductors with reduced widths allow smaller transistors to be designed, thereby increasing speed and reducing power requirements for the transistors.
Heretofore, lithographic tools are utilized to form transistors and other structures on the integrated circuit. For example, lithographic tools can be utilized to define gate conductors, active lines conductive lines, vias, doped regions, and other structures associated with an integrated circuit. Most conventional lithographic fabrication processes have only been able to define structures or regions having a dimension of 100 nm or greater.
In one type of conventional lithographic fabrication process, a photoresist mask is coated over a substrate or a layer above the substrate. The photoresist mask is lithographically patterned by providing electromagnetic radiation, such as, ultraviolet light, through an overlay mask. The portions of the photoresist mask exposed to the electromagnetic radiation react (e.g. are cured). The uncured portions of the photoresist mask are removed, thereby transposing and the pattern associated with the overlay to the photoresist mask. The patterned photoresist mask is utilized to etch other mask layers or structures. The etched mask layer and structures, in turn, can be used to define doping regions, other structures, vias, lines, etc.
As the dimensions of structures or features on the integrated circuit reach levels below 100 nm or 50 nm, lithographic techniques are unable to precisely and accurately define the feature. For example, as described above, reduction of the width of the gate conductor (the gate length) associated with a transistor or the of active line associated with an SOI transistor has significant beneficial effects. Future designs of transistors may require that the active line have a width of less than 50 nanometers.
Double gate SOI MOSFETs have received significant attention because of its advantages related to high drive current and high immunity to short channel effects. A double-gate MOSFET structure (FinFet) is discussed in xe2x80x9cSub 50-nm FinFet: PMOS,xe2x80x9d by Huang et al., 1999 IEDN. In addition, U.S. Pat. No. 5,889,302, issued to the assignee of the present application on Mar. 30, 1999, discusses a quadruple gate field effect transistor on an SOI substrate. The double-gate MOSFET and quadruple-gate MOSFET are able to increase the drive current because the gate surrounds the active region by more than one layer (e.g., the effective gate total width is increased due to the double or quadruple gate structure). However, patterning narrow, dense active regions is challenging. As discussed above with respect to gate conductors, conventional lithographic tools are unable to accurately and precisely define active regions as structures or features with dimensions below 100 nm or 50 nm.
Thus, there is a need for an integrated circuit or electronic device that includes smaller, more densely disposed active regions or active lines. Further still, there is a need for a ULSI circuit which does not utilize conventional lithographic techniques to define active regions or active lines. Even further still, there is a need for a non-lithographic approach for defining active regions or active lines having at least one topographic dimension less than 100 nanometers and less than 50 nanometers (e.g., 20-50 nm). Yet further still, there is a need for an SOI integrated circuit with transistors having multiple sided gate conductors associated with active lines having a width of about 20 to 50 nm.
An exemplary embodiment relates to a method of manufacturing an integrated circuit. An integrated circuit includes transistors. The transistors include a first transistor having a multi sided gate conductor disposed on at least two sides of an active line. The method includes removing portions of a mask layer above a substrate to form a mask feature, removing portions of an oxide material above the mask feature and the substrate to leave a spacer, removing the mask layer, and etching the substrate in accordance with the spacer. The mask feature has at least one sidewall. The spacer is disposed on the at least one sidewall. The active line is formed by etching the substrate in accordance with the spacer.
Another exemplary embodiment relates to a process of forming a gate conductor. The gate conductor is formed over at least two sides of an active line. The active line has a dimension less than one lithographic feature. The process includes providing a mask layer above a substrate, patterning the mask layer to have a sidewall, and providing an insulative spacer on the sidewall of the mask layer. The method also includes removing the mask layer, etching substrate in accordance with the insulative spacer to form the active line, and providing a conductive layer above the active line to form the gate conductor.
Another exemplary embodiment relates to a method of manufacturing a gate structure on an ultra-large scale integrated circuit. The gate structure covers a number of active lines. The active lines each have at least one dimension less than 50 nanometers. The method includes steps of lithographically patterning a mask layer above a substrate to have a plurality of islands, providing spacers on sidewalls of the islands, removing the islands, removing portions of the substrate in accordance with the spacers to form the active lines, and providing a conductive layer above the active lines as part of the gate structures. The islands have a minimum topographic dimension at least 50 nanometers wide.